Many high speed electronic systems operate with critical timing requirements that dictate a need to generate a periodic clock waveform possessing a precise timing relationship with respect to some reference signal. The improved performance of computing integrated circuits and the growing trend to include several computing devices on the same board present a challenge with respect to synchronizing the time frames of all the components.
While the operation of all components in the system should be highly synchronized, i.e., the maximum skew in time between significant edges of the internally generated clocks of all the components should be minimized, it is not enough to feed the external clock of the system to all the components. This is because different chips may have different manufacturing parameters, which, when taken together with additional factors such as ambient temperature, voltage, and processing variations, may lead to large differences in the phases of the respective chip generated clocks.
Synchronization can be achieved by using a timing circuit, such as a digital delay locked loop (DDLL) circuit, to detect the phase difference between clock signals of the same frequency and produce a digital signal related to the phase difference. DDLL circuits may require a relatively large number of clock cycles to synchronize. In conjunction with a DLL circuit, an open-loop topology may be used, such as a measure-controlled delay (MCD) circuit, where a timing measurement directly controls a variable delay. MCD circuits exhibit a fast lock capability (e.g., within 1-4 clock cycles after initialization). The MCD circuit generates an initial measurement, and the DDLL takes over to maintain the lock and track variations over time.